1. Field of the Invention
The present invention relates to a demultiplexer having a synchronization adjusting function used to separate a multiplexed signal in a communication system for processing a multiplexed high-speed signal, such as an optical communication system.
2. Description of the Related Art
In recent years, as an information amount is increased, a high-density information system such as an optical fiber communication system has been invented and put into practical use. In such a system, since a large amount of information can be transmitted even by a single signal line per unit time, signals of some media such as signals of an image and computer data are time-divisionally multiplexed. Therefore, a multiplexer for time-divisionally multiplexing data and a demultiplexer for demultiplexing and distributing the multiplexed data in accordance with its original data format serve as key devices. The multiplexer and the demultiplexer have been developed to increase their operation speeds, and a problem of matching with a communication system has been posed.
An example of a conventional demultiplexer is described in 1988 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 87-88, "A 4 Gb/s GaAs 16-1 Multiplexer/1-16 Demultiplexer LSI", M. Ida et al., 1988.
The demultiplexer described in this document is a 1:16 demultiplexer constituted by combining 1:2 demultiplexers each having a D flip-flop (DFF) and a tri-stage flip-flop (TS-FF) like a tree.
A general example of the DFF is an MS (master-slave) type DFF in which two R-S (reset-set) flip-flops (RS-FF) serve as a master stage and a slave stage, respectively. The TS-FF is an MS.sub.1 S.sub.2 type flip-flop obtained by adding another slave stage to the above MS (master-slave) type flip-flop. Although an input timing of this TS-FF is the same as that of the DFF, its output timing is shifted from a clock (CK) signal by a half period.
The above demultiplexer is obtained by connecting, like a tree, a plurality of 1:2 demultiplexers (branched at a ratio of 1:2 in units of stages) in which a pair of a DFF and a TS-FF are connected to receive an input signal in common so as to be expanded to be 1:16.
In order to process a high-speed signal, the number of processing sections where the signal having the highest speed is processed is preferably reduced as small as possible to obtain a stable operation. This is important especially to reduce manufacturing cost and the size of a device by using an IC arrangement. For this purpose, a circuit arrangement described here is suitable.
In a 1:2 demultiplexer as a basic element, a 1/2 CK signal obtained by frequency-dividing a CK signal corresponding to a input data signal by 1/2 is supplied to a TS-FF and a DFF, and the TS-FF and the DFF separate the data signals into two parts by independently performing latching at the rising and falling edges of the 1/2 CK signal.
FIG. 1 is a timing chart showing the basic 1:2 demultiplexer. Referring to FIG. 1, the TS-FF fetches a data string of (a, c, e, . . . ) since it latches an input signal consisting of a data string of (a, b, c, d, e, f, . . . ) at the rising (or leading) edge of a 1/2 CK. The DFF fetches a data string of (b, d, f, . . . ) since it latches the input signal at the falling (or trailing) edge of the 1/2 CK. Since an output from the TS-FF is delayed from the data fetching time by a half period, output timings of the TS-FF and the DFF are matched with each other. This is an operation of the basic 1:2 demultiplexer.
In a 1:16 demultiplexer in which the above 1:2 demultiplexers are expanded like a tree, data is changed at the same timing on all signal lines with respect to a plurality of input signals in stages from, e.g., the second stage. Therefore, a demultiplexing operation can be performed by a common 1/4 CK signal (obtained by frequency-dividing the 1/2 CK signal by 1/2), a common 1/8 CK signal (obtained by frequency-dividing the 1/4 CK signal by 1/2), and a common 1/16 CK signal (obtained by frequency-dividing the 1/8 CK signal by 1/2). A counter for frequency-dividing the CK signal outputs a output signal of one system for each of the 1/2, 1/4, 1/8, and 1/16 CK signals. Timings of the 1/2, 1/4, 1/8, and 1/16 CK signals must be adjusted in accordance with a delay time of a demultiplexer section as a main circuit to obtain an optimal operation. Separated data is sequentially output to each output signal terminal in accordance with the data order of an input signal data string.
A demultiplexer is a device for repeatedly performing an operation of determining a predetermined number of frames for data signals which are serial sequentially transmitted and distributing the data signals in the frames to different output terminals, thereby separating the data.
Signals to be transmitted in a high-density transmission system such as an optical communication system are a data string to be transmitted and a sync CK signal. When a signal is time-divisionally multiplexed, a signal at the start timing of a multiplexing frame is not transmitted, but a data signal having a predetermined pattern is transmitted. This pattern is checked to determine and correct the position of the multiplexing frame. This frame position is determined in accordance with a frequency-divided signal of a CK signal formed by the counter in the demultiplexer described above. For example, in the above-mentioned 1:16 demultiplexer, 16 types of uncertainty are present in a phase relationship between frequency-divided signals of sync CK signals and data signals. In a 1:8 demultiplexer, 8 types of uncertainty are present in a phase relationship between frequency-divided signals of sync CK signals and data signals.
As shown in FIG. 2, for example, assume that data of one byte (a.sub.0 to a.sub.7, b.sub.0 . . . ) is to be serially transmitted and parallel-converted (this operation is a kind of simple demultiplexing).
When data of one byte (a.sub.0 to a.sub.7, b.sub.0 . . . ) and a sync CK signal (bit sync signal) are simply input to a 1:8 demultiplexer (DEMUX), the data a.sub.0 to a.sub.7 are not always correctly output to output terminals D.sub.0 to D.sub.7. For example, as shown in FIG. 3B, the data a.sub.0 to a.sub.2 are output from the output terminals D.sub.5 to D.sub.7 at a certain timing, and the data a.sub.3 to a.sub.7 are output from the output terminals D.sub.0 to D.sub.4 at the next timing. In order to permit the output data to have significance in a system, the uncertainty mentioned above has to be eliminated. For this elimination, the relationships between the bits a.sub.0 to a.sub.7 of the data and the output terminals D.sub.0 to D.sub.7 must be predetermined, and the bits a.sub.0 to a.sub.7 of the data must be simultaneously output to the output terminals D.sub.0 to D.sub.7. To process data in this manner is referred to as frame synchronization.
In general, no countermeasure against this bit shift caused by uncertainty is available in an initial period of signal input, and the uncertainty remains the same. Therefore, a system must transmit an identification signal and perform correction when it determines the magnitude of a bit shift. However, such a correction method is not currently established. Simple possible methods are a method of skipping a CK signal by an arbitrary number of bits and a method of connecting an 8.times.8 matrix selector to the output terminals, thereby switching the output terminals by this selector. In the latter method using the selector, however, a system arrangement is too complicated. The former method of skipping a CK signal cannot satisfactorily cope with a high operation speed. In particular, at a frequency close to the limit of an operation speed of a DFF operation, it is very difficult to properly skip the CK signal by the above method. Therefore, the above method cannot be put into practical use under the present condition. Therefore, a demand has arisen for a method capable of outputting a signal distributed by a demultiplexer from predetermined output terminals by using a simple arrangement.
In recent years, a movement of international standardization of optical communication networks has progressed. Of the optical communication networks, an STS (Synchronous Transportation System) of a Synchronous Optical Network (SONET) is expected to be promising. In this network, since data is transmitted in unit of 8 bits, not one-bit multiplexing but 8-bit multiplexing must be performed. Since signal processing is performed after a signal is distributed into 8 bits in this network, a 1:8 demultiplexer is required. In the STS system, since the contents of data are changed when a bit shift occurs, frame synchronization must be reliably taken with respect to a data signal string. In frame synchronization, it is important to output 8 bits of a signal at the same timing to predetermined output terminals.
As is apparent from FIG. 3B described above, in the above-mentioned method of switching output signals, even though signals can be output to predetermined output terminals, a timing of some of the 8 bits is shifted, and a series of 8-bit signals are divisionally output twice.
That is, a high-speed multiplexer must transmit separated output signals to correct output terminals required by a system and perform frame synchronization at the same timing when a system is directed to the above STS system.